dlygate4s50 Delay Buffer 4-stage 0.50um length inner stage gates.

NAME

dlygate4s50 from sky130_fd_sc_lp

DESCRIPTION

Delay Buffer 4-stage 0.50um length inner stage gates.

FUNCTION

VERILOG

"sky130_fd_sc_lp__dlygate4s50"

/*
*/


`ifndef SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V

/**

`timescale 1ns / 1ps
`default_nettype none

`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
    X,
    A
);

    // Module ports
    output X;
    input  A;

    // Local signals
    wire buf0_out_X;

    //  Name  Output      Other arguments
    buf buf0 (buf0_out_X, A              );
    buf buf1 (X         , buf0_out_X     );

endmodule
`endcelldefine

`default_nettype wire
`endif  // SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V

SPICE

LAYOUT

sky130_fd_sc_lp__dlygate4s50_1

not to scale



.subckt sky130_fd_sc_lp__dlygate4s50_1 A VGND VNB VPB VPWR X
X0 VPWR a_27_52# a_288_52# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=500000u
X1 VGND a_27_52# a_288_52# VNB sky130_fd_pr__nfet_01v8 w=420000u l=500000u
X2 a_405_136# a_288_52# VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=500000u
X3 VGND a_405_136# X VNB sky130_fd_pr__nfet_01v8 w=840000u l=150000u
X4 VPWR a_405_136# X VPB sky130_fd_pr__pfet_01v8_hvt w=1.26e+06u l=150000u
X5 a_405_136# a_288_52# VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=500000u
X6 a_27_52# A VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X7 a_27_52# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=150000u
.ends