NAME

inputiso1n from sky130_fd_sc_hdll

DESCRIPTION

Input isolation, inverted sleep.

FUNCTION

X = (A & SLEEP_B)

VERILOG

"sky130_fd_sc_hdll__inputiso1n"
/*
*/


`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V

/**

`timescale 1ns / 1ps
`default_nettype none

`celldefine
module sky130_fd_sc_hdll__inputiso1n (
    X      ,
    A      ,
    SLEEP_B
);

    // Module ports
    output X      ;
    input  A      ;
    input  SLEEP_B;

    // Local signals
    wire SLEEP;

    //  Name  Output  Other arguments
    not not0 (SLEEP , SLEEP_B        );
    or  or0  (X     , A, SLEEP       );

endmodule
`endcelldefine

`default_nettype wire
`endif  // SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V

SPICE

LAYOUT

sky130_fd_sc_hdll__inputiso1n_1

not to scale



.subckt sky130_fd_sc_hdll__inputiso1n_1 A SLEEP_B VGND VNB VPB VPWR X
X0 VGND a_229_297# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X1 VPWR SLEEP_B a_27_53# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X2 VPWR a_229_297# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X3 VGND a_27_53# a_229_297# VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X4 a_319_297# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X5 a_27_53# SLEEP_B VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X6 a_229_297# a_27_53# a_319_297# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X7 a_229_297# A VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
.ends