/*
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
/**
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_V
not to scale
.subckt sky130_fd_sc_hdll__inputiso0p_1 A SLEEP VGND VNB VPB VPWR X
X0 a_211_413# a_27_413# a_307_47# VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X1 a_27_413# SLEEP VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X2 VGND a_211_413# X VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 VPWR a_211_413# X VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X4 VPWR a_27_413# a_211_413# VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X5 VGND SLEEP a_27_413# VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X6 a_211_413# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=180000u
X7 a_307_47# A VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
.ends