NAME

clkinvlp from sky130_fd_sc_hdll

DESCRIPTION

Lower power Clock tree inverter.

FUNCTION

VERILOG

"sky130_fd_sc_hdll__clkinvlp"
/*
*/


`ifndef SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V

/**

`timescale 1ns / 1ps
`default_nettype none

`celldefine
module sky130_fd_sc_hdll__clkinvlp (
    Y,
    A
);

    // Module ports
    output Y;
    input  A;

    // Local signals
    wire not0_out_Y;

    //  Name  Output      Other arguments
    not not0 (not0_out_Y, A              );
    buf buf0 (Y         , not0_out_Y     );

endmodule
`endcelldefine

`default_nettype wire
`endif  // SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V

SPICE

sky130_fd_sc_hdll__clkinvlp_2

not to scale


.subckt sky130_fd_sc_hdll__clkinvlp_2 A VGND VNB VPB VPWR Y
X0 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X2 VGND A a_150_67# VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
X3 a_150_67# A Y VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
.ends

sky130_fd_sc_hdll__clkinvlp_4

not to scale


.subckt sky130_fd_sc_hdll__clkinvlp_4 A VGND VNB VPB VPWR Y
X0 a_110_47# A Y VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
X1 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
X2 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X3 Y A a_268_47# VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
X4 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X5 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X6 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=250000u
X7 a_268_47# A VGND VNB sky130_fd_pr__nfet_01v8 w=550000u l=150000u
.ends