NAME

DESCRIPTION

FUNCTION

VERILOG

/*
*/


`ifndef SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V

/**

`timescale 1ns / 1ps
`default_nettype none

`celldefine
module sky130_fd_sc_hdll__a222oi (
    Y ,
    A1,
    A2,
    B1,
    B2,
    C1,
    C2
);

    // Module ports
    output Y ;
    input  A1;
    input  A2;
    input  B1;
    input  B2;
    input  C1;
    input  C2;

    // Local signals
    wire nand0_out ;
    wire nand1_out ;
    wire nand2_out ;
    wire and0_out_Y;

    //   Name   Output      Other arguments
    nand nand0 (nand0_out , A2, A1                         );
    nand nand1 (nand1_out , B2, B1                         );
    nand nand2 (nand2_out , C2, C1                         );
    and  and0  (and0_out_Y, nand0_out, nand1_out, nand2_out);
    buf  buf0  (Y         , and0_out_Y                     );

endmodule
`endcelldefine

`default_nettype wire
`endif  // SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V

SPICE

LAYOUT

not to scale

.subckt sky130_fd_sc_hdll__a222oi_1 A1 A2 B1 B2 C1 C2 VGND VNB VPB VPWR Y
X0 Y C1 a_117_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X1 a_117_297# B1 a_357_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X2 a_119_47# C2 VGND VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
X3 a_357_297# A1 VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X4 Y C1 a_119_47# VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
X5 a_357_297# B2 a_117_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X6 Y A1 a_627_47# VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
X7 VPWR A2 a_357_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X8 a_117_297# C2 Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=180000u
X9 a_449_47# B1 Y VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
X10 a_627_47# A2 VGND VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
X11 VGND B2 a_449_47# VNB sky130_fd_pr__nfet_01v8 w=640000u l=150000u
.ends