Skywater130 Factory Low Power

Key:
Useful for Analog Applications

Combinatorial

inv Inverter.
invlp Low Power Inverter.
invkapwr Inverter on keep-alive power rail.
nand2 2-input NAND.
nand3 3-input NAND.
nand4 4-input NAND.
nor2 2-input NOR.
nor3 3-input NOR.
nor4 4-input NOR.
o22ai 2-input OR into both inputs of 2-input NAND.
o2111ai 2-input OR into first input of 4-input NAND.
o21ai 2-input OR into first input of 2-input NAND.
o221ai 2-input OR into first two inputs of 3-input NAND.
o211ai 2-input OR into first input of 3-input NAND.
a22oi 2-input AND into both inputs of 2-input NOR.
a21oi 2-input AND into first input of 2-input NOR.
a221oi 2-input AND into first two inputs of 3-input NOR.
a211oi 2-input AND into first input of 3-input NOR.
a2111oi 2-input AND into first input of 4-input NOR.
a311oi 3-input AND into first input of 3-input NOR.
a31oi 3-input AND into first input of 2-input NOR.
a32oi 3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.
a41oi 4-input AND into first input of 2-input NOR.
o311ai 3-input OR into 3-input NAND.
o31ai 3-input OR into 2-input NAND.
o32ai 3-input OR and 2-input OR into 2-input NAND.
o41ai 4-input OR into 2-input NAND.

a2111o 2-input AND into first input of 4-input OR.
a211o 2-input AND into first input of 3-input OR.
a21bo 2-input AND into first input of 2-input OR, 2nd input inverted.
a21boi 2-input AND into first input of 2-input NOR, 2nd input inverted.
a21o 2-input AND into first input of 2-input OR.
a221o 2-input AND into first two inputs of 3-input OR.
a22o 2-input AND into both inputs of 2-input OR.
a2bb2o 2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.
a2bb2oi 2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR.
a311o 3-input AND into first input of 3-input OR.
a31o 3-input AND into first input of 2-input OR.
a32o 3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.
a41o 4-input AND into first input of 2-input OR.
and2b 2-input AND, first input inverted.
and2 2-input AND.
and3b 3-input AND, first input inverted.
and3 3-input AND.
and4bb 4-input AND, first two inputs inverted.
and4b 4-input AND, first input inverted.
and4 4-input AND.


xnor2 2-input exclusive NOR.
xnor3 3-input exclusive NOR.
xor2 2-input exclusive OR.
xor3 3-input exclusive OR.
nand2b 2-input NAND, first input inverted.
nand3b 3-input NAND, first input inverted.
nand4bb 4-input NAND, first two inputs inverted.
nand4b 4-input NAND, first input inverted.
nor2b 2-input NOR, first input inverted.
nor3b 3-input NOR, first input inverted.
nor4bb 4-input NOR, first two inputs inverted.
nor4b 4-input NOR, first input inverted.
o2111a 2-input OR into first input of 4-input AND.
o211a 2-input OR into first input of 3-input AND.
o21a 2-input OR into first input of 2-input AND.
o21ba 2-input OR into first input of 2-input AND, 2nd input inverted.
o21bai 2-input OR into first input of 2-input NAND, 2nd iput inverted.
o221a 2-input OR into first two inputs of 3-input AND.
o22a 2-input OR into both inputs of 2-input AND.
o2bb2a 2-input NAND and 2-input OR into 2-input AND.
o2bb2ai 2-input NAND and 2-input OR into 2-input NAND.
o311a 3-input OR into 3-input AND.
o31a 3-input OR into 2-input AND.
o32a 3-input OR and 2-input OR into 2-input AND.
o41a 4-input OR into 2-input AND.
or2b 2-input OR, first input inverted.
or2 2-input OR.
or3b 3-input OR, first input inverted.
or3 3-input OR.
or4bb 4-input OR, first two inputs inverted.
or4b 4-input OR, first input inverted.
or4 4-input OR.
maj3 3-input majority vote.

Multiplexer


mux2i 2-input multiplexer, output inverted.
mux2 2-input multiplexer.
mux4 4-input multiplexer.

Adder


fa Full adder.
fahcin Full adder, inverted carry in.
fahcon Full adder, inverted carry in, inverted carry out.
fah Full adder.
ha Half adder.

Isolators


iso0n ????.
iso0p ????.
iso1n ????.
iso1p ????.
isobufsrc Input isolation, noninverted sleep.
isolatch ????.
lsbuf ????.
lsbufiso0p ????.
lsbufiso1p ????.
inputiso0n Input isolator with inverted enable.
inputiso0p Input isolator with non-inverted enable.
inputiso1n Input isolation, inverted sleep.
inputiso1p Input isolation, noninverted sleep.
inputisolatch Latching input isolator with inverted enable.

Buffer


bufbuf Double buffer.
buf Buffer.
bufinv Buffer followed by inverter.
bufkapwr Buffer on keep-alive power rail.
buflp Buffer, Low Power.

Bus Driver and hold


busdriver2 Bus driver (pmos devices).
busdriver Bus driver (pmoshvt devices).
busdrivernovlp2 Bus driver, enable gates pulldown only (pmos devices).
busdrivernovlp Bus driver, enable gates pulldown only (pmoshvt devices).
busdrivernovlpsleep Bus driver, enable gates pulldown only, non-inverted sleep input (on kapwr rail).
bushold0 Bus signal holder (back-to-back inverter) with noninverting reset (gates internal node weak driver).
bushold Bus signal holder (back-to-back inverter) with noninverting reset (gates output driver).
busreceiver Bus signal receiver.

Clock

clkinv Clock tree inverter.
clkinvlp Lower power Clock tree inverter.

clkbuf Clock tree buffer.
clkbuflp Clock tree buffer, Low Power.
clkdlybuf4s15 Clock Delay Buffer 4-stage 0.15um length inner stage gates.
clkdlybuf4s18 Clock Delay Buffer 4-stage 0.18um length inner stage gates.
clkdlybuf4s25 Clock Delay Buffer 4-stage 0.25um length inner stage gates.
clkdlybuf4s50 Clock Delay Buffer 4-stage 0.59um length inner stage gates.

Buffer

ebufn Tri-state buffer, negative enable.

einvn Tri-state inverter, negative enable.
einvp Tri-state inverter, positive enable.

Flip Flops and Latches


dfbbn Delay flop, inverted set, inverted reset, inverted clock, complementary outputs.
dfbbp Delay flop, inverted set, inverted reset, complementary outputs.
dfrbp Delay flop, inverted reset, complementary outputs.
dfrtn Delay flop, inverted reset, inverted clock, complementary outputs.
dfrtp Delay flop, inverted reset, single output.
dfsbp Delay flop, inverted set, complementary outputs.
dfstp Delay flop, inverted set, single output.
dfxbp Delay flop, complementary outputs.
dfxtp Delay flop, single output.
dlclkp Clock gate.
dlrbn Delay latch, inverted reset, inverted enable, complementary outputs.
dlrbp Delay latch, inverted reset, non-inverted enable, complementary outputs.
dlrtn Delay latch, inverted reset, inverted enable, single output.
dlrtp Delay latch, inverted reset, non-inverted enable, single output.
dlxbn Delay latch, inverted enable, complementary outputs.
dlxbp Delay latch, non-inverted enable, complementary outputs.
dlxtn Delay latch, inverted enable, single output.
dlxtp Delay latch, non-inverted enable, single output.
dlybuf4s15kapwr Delay Buffer 4-stage 0.15um length inner stage gates on keep-alive power rail.
dlybuf4s18kapwr Delay Buffer 4-stage 0.18um length inner stage gates on keep-alive power rail.
dlybuf4s25kapwr Delay Buffer 4-stage 0.25um length inner stage gates on keep-alive power rail.
dlybuf4s50kapwr Delay Buffer 4-stage 0.50um length inner stage gates on keep-alive power rail.
dlygate4s15 Delay Buffer 4-stage 0.15um length inner stage gates.
dlygate4s18 Delay Buffer 4-stage 0.18um length inner stage gates.
dlygate4s50 Delay Buffer 4-stage 0.50um length inner stage gates.
dlymetal6s2s 6-inverter delay with output from 2nd stage on horizontal route.
dlymetal6s4s 6-inverter delay with output from 4th inverter on horizontal route.
dlymetal6s6s 6-inverter delay with output from 6th inverter on horizontal route.
edfxbp Delay flop with loopback enable, non-inverted clock, complementary outputs.
sdfbbn Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs.
sdfbbp Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.
sdfrbp Scan delay flop, inverted reset, non-inverted clock, complementary outputs.
sdfrtn Scan delay flop, inverted reset, inverted clock, single output.
sdfrtp Scan delay flop, inverted reset, non-inverted clock, single output.
sdfrtp_ov2 ????.
sdfsbp Scan delay flop, inverted set, non-inverted clock, complementary outputs.
sdfstp Scan delay flop, inverted set, non-inverted clock, single output.
sdfxbp Scan delay flop, non-inverted clock, complementary outputs.
sdfxtp Scan delay flop, non-inverted clock, single output.
sdlclkp Scan gated clock.

Sleep


sleep_pargate_plv ????.
sleep_sergate_plv connect vpr to virtpwr when not in sleep mode.
srdlrtp ????.
srdlstp ????.
srdlxtp ????.
sregrbp ????.
sregsbp ????.
srsdfrtn Scan flop with sleep mode, inverted reset, inverted clock, single output.
srsdfrtp Scan flop with sleep mode, inverted reset, non-inverted clock, single output.
srsdfstp Scan flop with sleep mode, inverted set, non-inverted clock, single output.
srsdfxtp Scan flop with sleep mode, non-inverted clock, single output.

Misc.


diode Antenna tie-down diode.
decapkapwr Decoupling capacitance filler on keep-alive rail.
tap Tap cell with no tap connections (no contacts on metal1).
tapvgnd2 Tap cell with tap to ground, isolated power connection 2 rows down.
tapvgnd Tap cell with tap to ground, isolated power connection 1 row down.
tapvpwrvgnd Substrate and well tap cell.
fill Fill cell.
conb Constant value, low, high outputs.
decap Decoupling capacitance filler.