Skywater130 Standard Cell and Primitives Overview

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Note that the information provided is for general guidance only. Refer to the Sky130 core repositories for engineering projects and remember that much of this hasn't yet been validated in silicon.

Intro

The OSU standard cells:
sky130_osu_sc_t18 OSU High Speed

Exploratory docs for the 7 factory libraries:
sky130_fd_sc_hvl High Voltage
sky130_fd_sc_hs High Speed
sky130_fd_sc_ms Medium Speed
sky130_fd_sc_ls Low Speed
sky130_fd_sc_lp Low Power
sky130_fds_sc_hd High Density
sky130_fds_sc_hdll High Density Low Leakage

General Observation

The high-density library uses smaller transistors that are more heavily doped to keep their performance up. This results in higher leakage, hence the provision of a low-leakage library where speed can be traded.

Similarities

None of the factory libraries provide transmission gates.

The combinatorial cells are provided in varying strength. Usually 1, 2, 4, 8 and 16x.

The cells all work down to 1.2v. The maximum voltage is 1.8v for all except the high-voltage library (5v).

Only the high-voltage library builds taps into the cells. For the rest the taps are expected to be added between cells using specialzed cells provided.

The circuit implementations in the libraries are conventional - basically the same ones you can find in the earliest successful CMOS ICs, the 4000A series.

The layouts for the high-speed, medium-speed and low-speed cells are nearly identical. Only the doping changes

Differences

The OSU library has weak inverter cells

The OSU library cells use thicker power rails than SKY130, in-cell well taps and horizontal wiring on Metal Layer 1.

The OSU cells have characterization with PEX extraction (forthcoming on SKY130)

OSU 18T track cells have higher drive-strength (larger transistors) than the corresponding SKY130

The output drive may be better balanced on the OSU cells (details to emerge when PEX completes) The OSU cells have more routing through M1, so M1 lines can be drawn horizontally across a DFF

The OSU cell will have IEEE 1801 features added.

Only the high-voltage library has a Schmitt trigger. This is presumably because the most common use of schmitt trigger is on an input pin. The high-voltage library has no clkinv and only the inv cells are available at different strengths.

The high-voltage and the high-density library provides level shifters to move signals between cells made to run at different voltages.

The low-power library has bus hold cells and some extra low power versions of the inverter and clock inverter. It also includes half-strength cell versions indicated with "_0". It also has matched ("_m") cell versions. Matching the size of p and n channel transistors provides the greatest power efficiency for low voltages.

Summary of Library Transistor Strength Differences

The data was extracted from the spice files for the inverter (inv) and clock inverter (clk) for each library.

The data is ordered by increasing density. This correlates with decreasing pmos width. Generally the pmos transistors take up at least twice the space as the nmos.

The dual Vt process allows for speed/power tradeoff and we see this reflected in the table by the changes in model for each type of transistor.

Leakage management is done by using longer pmos transistors.

The high-voltage library has much bigger transistors.

The low-power library has special extra low power inverters. The clkinv version of this is a interesting outlier. It uses wide and long pmos transistors and may be useful in providing an inverter building block for analog circuits because process variations are smaller on larger structures.

Library	T	VDD	Nand2			Raw Density	inv						clkinv						weak inverter
			Width um	Height um	Area um2	kgates/ mm2	pfet_			nfet_			pfet_			nfet_			pfet_			nfet_
							l	w	m	l	w	m	l	w	m	l	w	m	l	w	m	l	w	m
OSU
High Speed	18	1.2-1.8	1.43	7.2	10.296	97	150	3000	01v8	150	1000	01v8_lvt	150	3000	01v8	150	1000	01v8_lvt	150	2000	01v8	150	740	01v8_lvt
Medium Speed												01v8						01v8						01v8
Low Speed									01v8_hvt						01v8_hvt						01v8_hvt
High Speed	15			5.55	7.9365	126		2000	01v8		740	01v8_lvt		2000	01v8		740	01v8_lvt		1260	01v8		520	01v8_lvt
Medium Speed												01v8						01v8						01v8
Low Speed									01v8_hvt						01v8_hvt						01v8_hvt
TBD	12
TBD	9
Sky130
High Voltage	14	3.3-5.0	2.4	4.07	9.768	102	500	1500	rf_pfet_ g5v0d10v5	500	750	rf_nfet_ g5v0d10v5	Unavailable
High Speed	11	1.2-1.8	1.44	3.33	4.7952	209	150	1120	01v8	150	740	01v8_lvt	150	1680	01v8	150	420	01v8_lvt
Medium Speed
Low Speed									01v8_hvt			01v8			01v8_hvt			01v8
Low Power								1260			840								150	640	01v8_hvt	150	420	01v8	clkinv0
Low Power (invlp1, clkinvlp2)								630			420		250	2000			275		150	320	01v8_hvt	150	210	01v8	clkinvlp0
High Density	9		1.38	2.72	3.7536	266		1000			650		150	1680			420		250	2000	01v8_hvt	150	275	01v8	clkinvlp2
High Density Low Leakage			1.84	2.72	5.0048	200	180						180